RMAP IP Cores

STAR-Dundee offers a comprehensive range of SpaceWire and SpaceFibre IP cores used across the space industry in flight FPGAs and ASICs.

The SpaceWire Remote Memory Access Protocol (RMAP) standard provides a standard mechanism for reading from and writing to memory or registers in a remote SpaceWire or SpaceFibre node using RMAP formatted packets.  This simple but powerful capability is already designed into many components like the SpW-10X router and missions like Bepi-Colombo. The RMAP standard document is an ECSS standard, ECSS-E-ST-50-52C.

STAR-Dundee provides two independent IP cores that together implement the RMAP standard. The cores are listed below:

  • RMAP Target IP Core
  • RMAP Initiator IP Core

The Target IP core implements the remote memory access function. It decodes RMAP command packets, requests authorisation for the command, executes the transaction, and returns the command status and read command data in an RMAP reply packet. The Initiator IP core supports the generation of one or more RMAP transactions to either write to or read from a memory space. It encodes RMAP command packets, records outstanding transactions, and decodes RMAP replies.

Each core is provided as VHDL source code and is designed to operate with both the STAR-Dundee SpaceWire and SpaceFibre Interface IP cores. The RMAP cores can also be connected as a host port on a SpaceWire or SpaceFibre Routing Switch IP core. Standard AMBA AXI, AHB and APB interfaces are used to transfer packets, access memory and expose registers.

Further information on the RMAP IP cores can be found in the datasheet below, and for technical queries please enter any questions in the additional comments section of the quotation (becomes available once you click Request Quote). Alternatively, you may use the Quick Price Enquiry Form to ask any questions you have.

Product Features

  • Fully compliant with the SpaceWire RMAP Standard, ECSS-E-ST-50-52C

  • Compatible with SpaceWire and SpaceFibre IP cores

  • Provided as synthesisable VHDL source code

  • Configurable, supporting target device capabilities and application requirements

  • Standardised packet, memory and register access interfaces using AMBA AXI, AHB-Lite and APB protocols

  • Easily targeted to all major FPGA families including Microchip, Xilinx, Intel, Lattice, Frontgrade and NanoXplore

  • Support for radiation-tolerant device features included in Microchip RTAX, ProASIC3E/L, RTG4, PolarFire, Ultrascale and Ultrascale+, and Versal FPGA

  • Documented example designs are available for Microchip and Xilinx FPGA development kits. Please contact us for further information on other target devices or development kits

Technical Specs

  • Available Cores

    • RMAP Initiator

    • RMAP Target

  • Utilisation

    • RMAP Initiator:

      • 2897/1698/5 (LUT/FF/RAM) sites in Xilinx 7-Series, Zynq, Ultrascale, Ultrascale+ and Versal FPGA
      • 5569/2458/5 (COMB/FF/RAM) sites in Microchip RTAX FPGA
      • 27240/17 (CELL/RAM) sites in Microchip ProASIC3E/L FPGA
      • 4567/5301/5 (LUT/SLE/RAM) sites in Microchip RTG4, IGLOO2 and SmartFusion2 FPGAs
      • 8228/6864/5 (LUT/SLE/RAM) sites in Microchip PolarFire FPGA with Synplify TMR insertion enabled

    • RMAP Target:

      • 1401/1108/2 (LUT/FF/RAM) sites in Xilinx 7-Series, Zynq, Ultrascale, Ultrascale+ and Versal FPGA
      • 2769/1273/2 (COMB/FF/RAM) sites in Microchip RTAX FPGA
      • 15165/8 (CELL/RAM) sites in Microchip ProASIC3E/L FPGA
      • 2081/1119/2 (LUT/SLE/RAM) sites in Microchip RTG4, IGLOO2 and SmartFusion2 FPGAs
      • 4119/3546/2 (LUT/SLE/RAM) sites in Microchip PolarFire FPGA with Synplify TMR insertion enabled
  • Content

    • Supplied as VHDL source code including documentation, testbench with example operations, and documented example designs for common development kits.

  • Licencing options

    • Variety of licence and licence upgrade options available, any needs can be discussed with STAR-Dundee